For controlling the load of appliances such as cooling fans, low-wattage heaters, thermostats, low-wattage light sources, small electrical toys and test benches for loudspeakers, we need a power source whose voltage can be controlled in small steps and is capable of providing current of more than 1A. For that, we require low-resolution digital-to-analogue converters (DACs) with three to seven bits.
Here is the circuit capable of setting output voltage between 1.25V and 15V in 64 steps. The circuit can be adapted for a lot of applications.
Low-Cost 6-Bit DAC Circuit Diagram
Circuit and working
The circuit of the low-cost 6-bit DAC is shown in Fig. 1. The DAC is built around IC 7406, hex inverter (IC3). We may also use IC 7407 with six followers without changing the PCB. Steps are generated with the help of 6-bit digital input code D0 (LSB) through D5 (MSB) at CON2. Consequently, 64 combinations are possible starting from 000000 to 111111. At each combination, you will have a pre-determined output voltage between 1.25V and the possible maximum 15V.
Inputs D0 through D5 are TTL and CMOS compatible. These can be generated by microcontrollers, parallel-interface adapters such as PPI8255A, PIA6820/1 and Z80-PIO. In the simplest case, inputs can be driven with switches connecting inputs D0 through D5 to ground 0V or to 5V.
The size of the steps is programmable with trimmer potentiometers VR1 through VR6. Consequently, we can produce regular or irregular steps according to the need, depending on the characteristics of the load being controlled.
You can set any output voltage with any potentiometer between 1.25V and the maximum. For example, if you have a transformer for 18V AC, you can set outputs between 1.25V and around 15V with any potentiometer.
For adjustment in the simplest case, apply a set of seven test codes, as listed below, on CON2; output on CON3 will be as under.
Test code with 7406 (invert with 7407):
000000 Vout=Vmax (unadjustable)
000001 Vout=1.25V (VR1)
000010 Vout=3V (VR2)
000100 Vout=5V (VR3)
001000 Vout=7.5V (VR4)
010000 Vout=9V (VR5)
100000 Vout=12V (VR6)
The maximum output voltage on CON3 and CON4 is with code 111111 on the outputs of IC3 and depends on the input voltage of IC2. Please note that, if you use 7407, the codes will be non-inverted, and if you use 7406, the codes will be inverted.
The 6-bit input digital code D0 through D5 is buffered with 7406 or similar (IC3). With an open collector, the IC works as a translator/buffer between standard TTL levels to higher voltages needed for LM317.
Fig. 2: An actual-size PCB layout of the low-cost 6-bit DAC
Fig. 3: Component layout of the PCB
If the requirement of current is more than 1A, then select adjustable regulator IC2 from series LM317T (1.5A), LM350 (3A) or any compatible adjustable-linear regulator.
This makes the DAC adaptable to a lot of applications. In many cases, there is no need to start the output voltage from 0V. This makes the solution even simpler.
Input digital code D0 through D5 is buffered with IC3, which should be obligatory with open connector. The preferred device is 7406 or better, with outputs that can work with up to 30V.
Power requirements are from a common configuration built around step-down transformer X1 (secondary voltage 18V to 20V with current 1A or above), bridge rectifier BR1 and voltage regulator IC 7805 (IC1). The mains power is applied on connector CON1. 5V is available at connector CON5.
The selection of mains transformer X1, bridge rectifier and heat sinks for IC1 and IC2 depends on the required maximum output current from the DAC. IC1 and IC2 can be mounted on a common heat-sink after proper mounting is done.
The load is connected to connector CON3. A DC voltmeter with 50V range is connected at CON4 for measuring the output voltage. The DAC can be tested with 12V/5W/0.4A light bulb, 12V/0.3A fan, heating element for thermostat with nominal current up to 0.3A and maximum current below 1A and similar loads.
Construction and testing
An actual-size, single-side PCB layout for the low-cost 6-bit DAC is shown in Fig. 2 and its component layout in Fig. 3.
Sourced By: EFY Author: Petre TZV Petrov
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