This circuit is a voltage monitor which operates on fixed testes ± 5 VDC and ± 12 VDC, and is easily constructed as shown in Fig. It is considerably simpler than the normal display using comparators and AND gates. The circuit is not intended to indicate the level of entries. If one of the testes fail, for example, -5 V line fails, the transistor Q3 remains on but the base-emitter junction of T2 is not, so that this transistor is cut off. When this happens, there is no current through D, which then turns off.
Monitor voltage + and - 5VDC + and - 12VDC Circuit Diagram
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